1. Field of the Invention
The present invention relates to a substrate processing method and a program for causing a computer to execute the substrate processing method.
2. Description of the Related Art
In a process of forming, for example, a multilayer wiring structure of a semiconductor integrated circuit or the like, processing of forming an insulating film between metal wirings on a wafer is performed. For the processing of forming the insulating film, a coating method is widely used which applies a liquid insulating film material onto the wafer, rotates the wafer to diffuse the insulating film material over the wafer surface, and then hardens the insulating film material. The coating method is used to form an SOG (Spin On Glass) film or an SOD (Spin On Dielectric) film as the insulating film. With the coating method, a flat film can be easily formed as compared with the CVD (Chemical Vapor Deposition) method which is similarly widely known.
However, since the amount of the insulating film material entering the depressions varies due to the depth of steps and roughness of a base pattern even by the above-described coating method, projections and depressions may be formed on the front surface of the formed insulating film. Once the projections and depressions are formed on the front surface of the insulating film, focus is not partially achieved on the resist film at the upper layer at the time of exposure of the photolithography process, resulting in non-uniformity in the line width of the resist pattern and the etching width of the insulating film. Further, during the etching step, a situation occurs in which the depth of the etched trench differs between a portion with a large thickness and a portion with a small thickness of the insulating film. As a result, the metal wiring embedded in the trench in the insulating film differs in length and thickness, leading to non-uniformity in electric resistance of the wirings within the wafer. Thus, the formation of the projections and depressions on the front surface of the insulating film causes various troubles in the process of forming the multilayer wiring structure.
Hence, the CMP (Chemical Mechanical Polishing) processing to planarize the insulating film is performed after the insulating film is applied and hardened. The CMP processing is performed by bringing a polishing pad into contact with the wafer front surface while supplying a liquid slurry containing silica particles (a polishing liquid) to polish the wafer front surface in a CMP apparatus (Japanese Patent Application Laid-open No. 2004-106084).
However, the above-described CMP apparatus employs a polishing pad twice or larger than the wafer, and therefore is very large in size and also consumes a large amount of power. In addition, the apparatus uses a large amount of expensive slurry, leading to increased running cost. Furthermore, if the slurry remains on the wafer, it may contaminate or scratch the multilayer wiring. Therefore, a cleaning step performed by a cleaning unit for washing away the slurry is separately required, resulting in more complicated processing steps.